Line 1: SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO '1';Line 2: SIGNAL a: BIT;Line 3: SIGNAL b: STD_LOGIC;Line 4: SIGNAL c: my_logic;Line 5: b=a;Line 6: b=c;Find out the error - Aisiri p

Aisiri p

Line 1: SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO '1';Line 2: SIGNAL a: BIT;
Line 3: SIGNAL b: STD_LOGIC;
Line 4: SIGNAL c: my_logic;
Line 5: b=a;
Line 6: b=c;

Find out the error

Engineering-IT Engineering-IS Engineering-CS Engineering-AI Engineering Placement Engineering - AI ML Software engineering Programming Programmer Analyst Analogy VHDL

Posted on by

Views

Comment(s)

Please Login to post your answer or reply to answer

Recent MCQ Comments

Top Scored MCQs

Scroll